Implementation and Performance Analysis of a Single Phase Synchronization Technique based on T/4 Delay PLL

Abstract

The proper operation of current controllers in the grid tie inverters strongly depend on the accuracy of grid phase detection algorithm of the phase locked loop system. The main aim of this paper is to design and implement a single phase synchonization technique base on T/4 delay PLL. In this work,  the real time T/4 delay PLL algorithm is realized by using fixed point arithmetic computation technique that embedded in the 16 bit-wide digital signal controller dsPIC30f401. The focus of our research is to investigate the effect of the PLL control bias to the PLL ouput performance mainly in the steady state conditions. Based on the experimental results, the accuracy of the phase detection algorithm practically could be achieved by utilizing a relatively high control bias even with  just using a simple proportional controller. Whereas, for a relatively low control bias, the accurate phase detection could be achieved by utilizing a proportional integral controller.